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SIL & SIS Basics

A SIF reduces risk by a target amount — the required SIL comes from the risk; design must prove it.

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Quick pick (TL;DR)
  • Determine the target SIL from the risk (LOPA) — SIL 1 to 4, each a 10× reduction in failure probability.
  • Each SIL maps to a Risk Reduction Factor and an average Probability of Failure on Demand (PFDavg).
  • Build the SIF (sensor + logic solver + final element), pick voting (1oo2, 2oo3) and a proof-test interval, then verify the calculated PFDavg meets the target and the architecture meets the hardware-fault-tolerance constraint.
  • Keep the SIS independent of the basic control system.

Step 1 — SIL targets

SILRRFPFDavgTypical
SIL 110–10010⁻¹–10⁻²Minor
SIL 2100–1,00010⁻²–10⁻³Serious
SIL 31,000–10,00010⁻³–10⁻⁴Severe
SIL 410,000–100,00010⁻⁴–10⁻⁵Rare

Step 2 — Worked SIL verification

High-pressure trip, SIL 2
Step 1 — Target unmitigated risk too high by ~300× → need RRF ≥ 300 → SIL 2 Step 2 — Build the SIF sensor : 2 × pressure Tx, 1oo2 logic : safety PLC (SIL3 capable) final : ESD valve + solenoid, 1oo1 + PST Step 3 — Sum PFDavg PFD_sensor (1oo2) = 0.0005 PFD_logic = 0.0007 PFD_final (+PST) = 0.0030 PFDavg total = 0.0042 (4.2E-3) Step 4 — Check RRF = 1/0.0042 = 238 10⁻³ ≤ 4.2E-3 < 10⁻² → SIL 2 met

The valve dominates PFD — PST & voting reduce it. Both the PFDavg band AND HFT must pass.

Step 3 — Architecture & lifecycle

  • 1oo2 safer; 2oo3 balanced; 2oo2 fewer trips.
  • Shorter proof tests & PST lower PFDavg.
  • SIS independent from BPCS.

PFDavg / SIL calculator

Loop PFDavg → RRF → SIL band
PFDavg = Σ subsystems; RRF = 1/PFDavg → SIL band.
PFDavg gate only — also meet the HFT constraint & keep SIS independent.

Common mistakes

  • SIL claimed from device certs alone.
  • Sharing devices with BPCS.
  • No proof-test plan.

Requisition & datasheet

  • SIF, consequence, target SIL.
  • Architecture, voting, PFDavg, HFT.

Frequently asked questions

What should I know about SIL & SIS Basics?

Determine the target SIL from the risk (LOPA) — SIL 1 to 4, each a 10× reduction in failure probability. Each SIL maps to a Risk Reduction Factor and an average Probability of Failure on Demand (PFDavg). Build the SIF (sensor + logic solver + final element), pick voting (1oo2, 2oo3) and a proof-test interval, then verify the calculated PFDavg meets the target and the architecture meets the hardware-fault-tolerance constraint. Keep the SIS independent of the basic control system.

Which standards or codes apply?

IEC 61511 (process-sector functional safety / SIS), IEC 61508 (base standard), ISA 84, plus LOPA methodology for SIL determination.

Standards — IEC 61511; IEC 61508; ISA 84; LOPA.

Related guides

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